1. Field of the Invention
The present invention relates to a storage electrode of a semiconductor device and a method of forming the storage electrode. More particularly, the present invention relates to a cylindrical storage electrode of a semiconductor memory device, e.g., a dynamic random access memory (DRAM) device, which is used for storing data, and a method of forming the storage electrode.
2. Description of the Related Art
Generally, a semiconductor memory device, such as a DRAM device, stores information, e.g., data, program orders, and the like. The information may be read from the semiconductor memory device and other information may be additionally stored in the semiconductor memory device. The semiconductor memory device may include one transistor and one capacitor.
The capacitor in the DRAM device may include a storage electrode, a dielectric layer and a plate electrode. To improve capacity of the memory device including the capacitor, a capacitance of the capacitor is increased. Particularly, when the capacitance of the capacitor is increased, a read capacity of the memory device is improved and an error ratio generated in the memory device is reduced, thereby improving memory characteristics of the memory device.
However, as memory devices have become more highly integrated, forming a capacitor having a sufficient capacitance in a cell having very small area has become increasingly difficult. To overcome the above difficulty, various methods have been studied.
Examples of these methods include a method of increasing a height of a capacitor and a method of expanding an effective area of a cell using a hemispherical silicon grain (HSG), among others.
According to the method of increasing the height of the capacitor, however, the higher a storage electrode is, the thicker a mold layer for a mold is required to be. When an opening filled with the storage electrode is formed through an insulation layer by a dry etching process, the opening has a bottom width narrower than a top width due to the thick mold layer. As a result, the storage electrode has a shape corresponding to that of the opening. More specifically, the storage electrode has a bottom width narrower than a top width, thereby shortening an interval between adjacent storage electrodes. As a result, adjacent storage electrodes lean so that a 2-bit error between adjacent storage electrodes may be generated and also the leaning storage electrodes contact each other, thereby generating an electrical short between adjacent storage electrodes.
According to the method using the HSG, a HSG layer having an uneven shape is formed on a storage electrode. However, pieces are fractured from the HSG layer or coarse polysilicon grains grow from the storage electrode during formation of the HSG layer so that the pieces or the coarse polysilicon grains may contact an adjacent storage electrode, thereby generating an electrical short between adjacent storage electrodes.
According to a conventional method for overcoming such an electrical short, a storage electrode includes a doped amorphous silicon layer and an undoped amorphous silicon layer. An upper portion of the storage electrode is partially removed using an etching selectivity between the silicon layers to form a HSG layer.
However, since the HSG layer is formed by etching the storage electrode including substantially identical materials, the etching selectivity may be relatively low. Therefore, forming the HSG layer to have a wide surface area may be difficult.